Synchronising method for data processing system esp. time data

摘要

Each module has private registers TBR and communication element PKC with register TBC. A processor (10, etc.) is chosen as system master which controls other processors (11, etc.). It remains in a ready state so that the states of every other processor (11) waiting for data from master processor are not interrupted. Every processor, which is free to receive, reads the contents of TBC register that is linked to processor of same module (1, 2). It writes content in its TBR register (16, etc.) without being able to be interrupted. System holds a data value and through it increments clock register.