Clock signal or carrier signal recovery circuit for digital data signal

摘要

The circuit includes a clock oscillator (3) with an adder in a feedback loop for adding the digital data signal to the oscillator signal. The adder has at least one input (6,6') for the digital data signal. The input is connected to a phase detector which also receives the oscillator signal. The phase angle of the oscillator can be adjusted to match that of the data signal.