发明名称 |
Data processing system register control |
摘要 |
A data processing system having a plurality of registers 10 and an arithmetic logic unit 20, 22, 24 is responsive to program instruction words. At least one program instruction word includes a destination register bit field <dest> specifying a destination register of a result data word and a destination register write disable flag for disabling writing of that result data word to the destination register. |
申请公布号 |
US5881257(A) |
申请公布日期 |
1999.03.09 |
申请号 |
US19960727312 |
申请日期 |
1996.10.08 |
申请人 |
ARM LIMITED |
发明人 |
GLASS, SIMON JAMES;JAGGAR, DAVID VIVIAN |
分类号 |
G06F9/302;G06F9/318;G06F9/32;G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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