| 摘要 |
In the present invention data from the odd memory cell array is latched to a data-hold circuit at a fast timing, which ignores the delay time of the +1 arithmetic circuit, and outputs that data to the output terminal. Further, when the supplied column address is even, data from the even memory cell array is latched to a data-hold circuit at a fast timing similar to that described above, and when the column address is odd, this data is latched to a data-hold circuit with a delay equivalent to the delay of the +1 arithmetic circuit. In this case, since the output of even output data to an output terminal occurs following the output of odd output data, the overall output operation is not affected comparing to the conventional one. Another aspect of the present invention provides a circuit, which shifts one bit combinations of the second and third bits following the least significant bit in a column address. And when the column address is even, the second and third bits address as-is are supplied into an even decoder, and when the column address is odd, supplies a shifted combination of the second and third bits address are supplied to the even decoder. Since this shift operation does not require the same delay time as conventional arithmetic operations, both even and odd CAS delay times can be reduced.
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