| 摘要 |
Power reduction is achieved either statically or dynamically within domino logic circuits. For static power reduction, representative input signals to the logic circuit are analyzed and any variation from purely random signals is detected. The domino circuit is then configured, if possible, to utilize less power for input signals having a higher probability of being received. As an example, a domino adder circuit is configured with predischarged carry nodes, rather than precharged carry nodes, individual logic cells to exploit input signals which often include numerous leading zeros. For dynamic power reduction, actual individual input signals are analyzed to determine whether power reduction can be achieved by either selecting between two preconfigured domino circuits or by modifying the input signals prior to routing through a single domino logic circuit. In the latter case, inversion of the input signals may result in power savings. In a specific example, a domino adder is provided. The input signals are analyzed to determine the percentage of pairs of ones or zeros in the input signals. If primarily composed of zeros, the input signals are routed through a domino circuit configured with logic cells with predischarged carry nodes. If the input signals are primarily ones, the signals are inverted, then routed through the domino circuit. Method and apparatus embodiments of the invention are described.
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