| 摘要 |
PROBLEM TO BE SOLVED: To reduce the load capacity of a COMP signal becoming the result of defective memory cell detection. SOLUTION: Complemental signals (address signals A0T-A3T and inversion address signals A0N-A3N) every each bit of respective addresses are wired to obtain respective gate signals of transistors Tr1-Tr4. Whereby, the number of transistors Tr1-Tr4 making the level of the COMP signal becoming the result of the defective memory cell low is reduced to half compared with a conventional one. |
