| 摘要 |
PROBLEM TO BE SOLVED: To reduce the maximum consumption current due to the charging and discharging of parastic capacitances of data busses or an avarage consumption current in a burst by deciding whether the polarity of data to be transmitted is→to be inverted or not based on the level of the least significant address of an internal address signal at the time of transmitting the data from a consecutive first section to a second section of data busses. SOLUTION: This memory is provided with a circuit means consisting of inverters I1, I2 and N-channel type transistors TG1, TG2 inverting the polarity of data to be transmitted or transmitting the data as it is based on the level or the least significant address IYO of the internal address signal in the transmitting of the data from a consecutive first section WBUST1 to a second section WBUST2 of the data busses. Thus, since the switching of a level is generated in only one section in among the WBUST1 and the WBUST2, only either of parastic capacitances C1, C2 is charged and discharged and current to be consumed in the sections WBUST1, WBUST2 can be reduced.
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