| 摘要 |
A communication system which includes more efficient bus utilization for higher data throughput. The communication system includes various logic devices connected to a system bus. The communication system intelligently utilizes unused system bus bandwidth for improved performance. The communication system includes a receive buffer, a memory, a central processing unit (CPU), a direct memory access (DMA) controller, and a bus arbiter each preferably coupled to the system bus. The buffer is operable to generate a low priority DMA transfer request when any amount of data is stored in the buffer. The buffer is also operable to generate a high priority DMA transfer request when a certain threshold or amount of data is stored in the buffer, i.e., when a certain "water-level" has been reached. When the buffer generates the low priority DMA request, the DMA controller and/or bus determine if the system bus is otherwise not being utilized, e.g., if the CPU is currently operating out of its cache system and no other devices have requested or are using the bus. If so, the DMA transfers are allowed to proceed. The high priority DMA transfer request operates normally, guaranteeing access to the system bus to avoid FIFO overruns.
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