发明名称 Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from semantic specifications and descriptions thereof
摘要 A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized.
申请公布号 US5880971(A) 申请公布日期 1999.03.09
申请号 US19970905917 申请日期 1997.08.04
申请人 LSI LOGIC CORPORATION 发明人 DANGELO, CARLOS;NAGASAMY, VIJAY KUMAR;BOOTEHSAZ, AHSAN;RAJAN, SREERANGA PRASANNAKUMAR
分类号 G06F9/44;G01R31/317;G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F9/44
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