| 摘要 |
PROBLEM TO BE SOLVED: To process overlapped requests by providing another inter-connection network for transferring a coherency report between plural processor units, totaling the reports of all the units, and transmitting it to the origin of a coherent read request. SOLUTION: For example, when data whose load instruction is issued by a CPU core 11 are not present in a cache 12 of processor boards 10-0 and 10-1, a cache access control circuit 21 judges it as cache miss, and a transaction transmitting circuit 22 transmits a data read transaction to a cross bar unit 40, and the cross bar unit 40 transmits it to the processor boards 10-0 and 10-1 and a designated memory board 60-0. The processor boards 10-0 and 10-1 which receive a coherent read request inspect the state of an inside cache 12, and report it to a coherency report unit 50. The coherency report unit 50 totals all the reports, reports it to the processor board 10-0, and communicates data transfer permission to the memory board 60-0. |
