发明名称 |
Method and apparatus for improving wireability in chip modules |
摘要 |
A method of making a laminated structure includes forming a first lamination having first and second conductive layers having inner and outer surfaces and being spaced apart by a dielectric layer, drilling through the first conductive layer and dielectric layer to form a blind via having a bottom coexistent with the inner surface of the second conductive layer, plating the blind via with a conductive material, and patterning the second conductive layer to form at least one contact pad over the blind via.
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申请公布号 |
US5879787(A) |
申请公布日期 |
1999.03.09 |
申请号 |
US19960747171 |
申请日期 |
1996.11.08 |
申请人 |
W. L. GORE & ASSOCIATES, INC. |
发明人 |
PETEFISH, WILLIAM GEORGE |
分类号 |
H01L23/12;H01L21/48;H01L23/498;H05K1/00;H05K1/05;H05K1/11;H05K3/00;H05K3/42;H05K3/44;(IPC1-7):B32B9/00 |
主分类号 |
H01L23/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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