| 摘要 |
A fourth impurity region having a smaller junction depth than that of the second impurity region, and having a third impurity concentration which is lower than that of the second impurity region is formed between the first impurity region and second impurity region. A fifth impurity region whose junction depth is smaller than that of the second impurity region, and having a third impurity concentration is formed between the first impurity region and second impurity region. Since the intensity of the electric field applied to the drain region is reduced, transistor characteristics are improved. Also, the integration of a semiconductor device is increased by reducing the layout space.
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