发明名称 CMOS MULTIPLIER AND BI-CMOS MULTIPLIER
摘要 PROBLEM TO BE SOLVED: To provide a CMOS multiplier and a Bi-CMOS multiplier which can actualize complete linear operation with simple circuitry configuration. SOLUTION: Three transistors are driven by a main constant-current source I0 from their drains, the gate of a 1st transistor M1 and the gate of a 2nd transistor M are connected in common, and a 1st input pair are constituted with the gate of a 3rd transistor. A 2nd input pair are composed of the gate of a 4th transistor M4 and the gate of a 5th transistor M5. A current source M10 which is biased by a source follower transistor M9 driven by a subordinate constant-current source Ib is connected to the source of the 3rd transistor, current mirror circuits M7 and M8, and M12 and M13 which are biased by source follower transistors M6 and M11 driven by the subordinate constant- current source are connected to the source of the 1st and 2nd transistors, and an output pair consist are constituted together with a current source.
申请公布号 JPH1166214(A) 申请公布日期 1999.03.09
申请号 JP19970228570 申请日期 1997.08.25
申请人 NEC CORP 发明人 KIMURA KATSUHARU
分类号 G06G7/163;G06G7/164;(IPC1-7):G06G7/163 主分类号 G06G7/163
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