| 摘要 |
To eliminate the momentary drop of the positive power supply due to instantaneous discharge of floating nodes of NOR gates in a sub-decoder to improve rising up of word lines of a semiconductor memory, a NOR gate of the invention comprises a serial connection of two pMOS transistors (MP1 and MP2), a parallel connection of two nMOS transistors (MN1 and MN2) and a nMOS transistor (MN3) for bypassing floating charge of connection point of the two pMOS transistors. The serial connection of the pMOS transistors and the parallel connection of the nMOS transistors are connected between a positive power supply (Vcc) and a negative power supply (Vss). A main decoder signal (S1) gates one of the pMOS transistors connected to the positive power supply, one of the parallel connection of the nMOS transistors and the nMOS transistor for bypassing the floating charge. A pre-decoder signal (S2) gates other MOS transistors. A word line (WL) is connected to connection point between serial connection of the pMOS transistors and the parallel connection of the nMOS transistors. <IMAGE> |
