The cascade MOS thyristor has an insulated gate bipolar transistor in a first cell (B) and a thyristor in a main cell (A) connected together so that they provide a lateral FET with a channel of given conductivity type. The emitter zone (9) of the thyristor has an embedded layer (15) for enhancing the charge carrier recombination rate, for reducing the switching resistance of the cascade MOS thyristor.
