| 摘要 |
<p>A variable block size 2-D IDCT engine (10) which can compute any arbitrary mix of transforms. A first 1-D IDCT processor (20a) computes the transform of the data block by columns and stores the intermediate results in a transposition memory. A second 1-D IDCT processor (20b) computes the transform of the intermediate results by rows. Different mix of transforms can be easily performed by correctly ordering the input data, selectively combining the input data before the butterfly stages, and controlling the additions and multiplications at each stage of butterfly. The unnecessary butterflies are placed in the bypass mode. The butterflies can be implemented with serial adders (56) and bit-serial multipliers to greatly simplify the hardware design and minimize the routing requirements between successive stages of butterfly. The fully pipelined structure allows the IDCT engine to maintain a throughput rate of one pixel per clock cycle.</p> |
