发明名称 |
Parallel hierarchical timing correction |
摘要 |
A method is provided for performing timing correction on a hierarchical integrated circuit design comprising the steps of forming a hierarchical integrated circuit design, applying a hierarchical timing tool to the entire circuit hierarchy, applying a timing correction algorithm to improve timing of the design as measured by the hierarchical timing tool; and applying a parallel timing management tool to multiple applications of the hierarchical timing tool and the timing correction algorithm. Also described is an information handling system including means for implementing the parallel hierarchical timing correction method of the present invention.
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申请公布号 |
US5877965(A) |
申请公布日期 |
1999.03.02 |
申请号 |
US19960671030 |
申请日期 |
1996.06.24 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HIETER, NATHANIEL DOUGLAS;HINES, CHARLES KENNETH;LEONARD, TODD EDWIN;OSLER, PETER JAMES |
分类号 |
G06F17/50;(IPC1-7):G06F9/455;H01L21/70;H01L27/02 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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