发明名称 Viterbi decoding apparatus and viterbe decoding method
摘要 Survivor sequences information is supplied to a RAM 61-1 and a RAM 61-2 as an input Din. The RAM 61-1 and the RAM 61-2 perform an interleaving operation and store the survivor sequences information alternately in accordance with a clock CK1 and a clock CK2 differing in phase from the clock CK1 by half a period. The phases of the clock CK1 and the phase of the clock CK2 are delayed by half a period when a write operation is switched to a read operation with data being outputted at a selector 62 in an appropriate order accordingly. Traced-back data is then inputted from terminal A and terminal B to the selector 62 and outputted from a terminal X after one of these items of data has been selected at a prescribed timing.
申请公布号 US5878060(A) 申请公布日期 1999.03.02
申请号 US19970822501 申请日期 1997.03.24
申请人 SONY CORPORATION 发明人 WAKAMATSU, MASATAKA
分类号 H03M13/23;H03M13/41;(IPC1-7):H03M13/12 主分类号 H03M13/23
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