Differential analog-to-digital converter with low power consumption

摘要

An analog-to-digital (A/D) converter capable of receiving a differential input for improved noise rejection and having two static resistive ladders for reducing power consumption. The resistive ladders are anti-parallel and have a high impedance, each dividing fixed voltages into a group of reference voltages. A first stage of comparators compares the positive signal of the differential input with each of the reference voltages from one of the resistive ladder, and the negative input signal with each of the reference voltages from the other resistive ladder. The outputs of the first stage of comparators are compared by a second stage of comparators to generate a group of binary outputs in parallel. An encoder converts the outputs of the second-stage comparators into a digital value. Decoupling capacitors are also provided to reduce the AC impedance of the resistive ladders.