CLOCK SKEW DIAGNOSTIC CIRCUIT

摘要

PROBLEM TO BE SOLVED: To evade the influence of skew between blocks in clock tree synthesis between hierarchies of an LSI constituted in hierarchical structure. SOLUTION: The distribution clock output of a global tree 21 having the clock distributing function of the 1st layer and the respective outputs of 2nd- layer local trees 26 to 28 in respective blocks which have a lower-layer clock distributing function are ANDed by AND gates 39 to 41 and then signals which are in inverse proportion to the delay times of respective clocks are obtained in those gate outputs 42 to 44. The clock skew can be monitored by observing those signals and the clock skew between blocks is deleted by performing delay quantity control over the clock signals by delay control circuits 50 to 52 according to those signals.