| 摘要 |
PROBLEM TO BE SOLVED: To obtain a phase-locked loop circuit that realizes wide capture range, low cut-off frequency of a jitter transfer characteristic and low rms jitter by extracting a DC component from an output signal of a frequency difference detection circuit, adding the extracted component to a DC component of a phase comparison signal of the PLL and giving the sum to a 1st voltage controlled oscillator. SOLUTION: This PLL 10 uses a phase comparator 11 for comparing the phase of an input signal with an output signal of a 1st VCO 13, an LPF 12 extracts the DC component of a phase comparison signal and the extracted signal is fed back to the 1st VCO 13. A frequency difference detection circuit 20 provides an output of a DC voltage, in response to a frequency difference between the input signal and an output signal from a 2nd VCO 21 and feeds the voltage back to the 1st VCO 13. The frequency detection circuit 20 has a conversion gain that outputs a DC voltage specified by a capture range which is the requirement of an operation margin. Thus, a low cutoff frequency in a jitter transfer characteristic is realized by combining the PLL 10 and the frequency difference detection circuit 20. |
