| 摘要 |
PROBLEM TO BE SOLVED: To form a dynamic RAM wherein high scale integration and low consumption power are enable, by a method wherein a subword selection line is arranged to a plurality of subarrays, passing on the subarrays. SOLUTION: Every two memory arrays are arranged on the left and the right of the longitudinal direction of a semiconductor chip. An address input circuit, a data input and output circuit, and an input and output interface circuit constituted of a bonding pad row, etc., are arranged on the center part 14, and column decoder regions 13 are arranged on parts in contact with the memory arrays. Main row decoder regions 11 are arranged on the upper and lower central parts to the longitudinal direction, main word driver regions 12 are formed on and under the main row decoder regions 11, and main word lines of vertically divided memory arrays are driven, respectively. Thereby a practical threshold voltage value can be increased, a subthreshold leakage current can be reduced, special isolation of a P-type well region in which the direct peripheral circuits are formed is unnecessary, and high scale integration is enabled. |
