| 摘要 |
An array of static random access memory (SRAM) cells is configured for presetting to a particular value without the need to write to each cell in the array. Address line controllers are provided which are responsive to preset, read, and write signals. If a write control signal is asserted, the address line controllers maintain an asserted state on their address lines, so that a subsequent read cycle will output the written memory cell contents. However, if the memory cells in the array have not been written to, the address line controllers deassert their address lines, and simultaneously enable preset setting cells, so that a subsequent read cycle will output the logic state of the setting cells, rather than the contents of the array memory cells.
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