Information processing system

摘要

Disclosed is a computer system that includes a CPU that can be operated both in a normal mode and in a power saving mode. The system further includes at least one peripheral device and a bus for allowing communication between the CPU and the peripheral device. A bus cycle detector monitors a bus cycle on the bus and a condition determiner determines the operation mode for the CPU in a specific bus cycle that is detected by the bus cycle detector. A signal generator is used to provide to the CPU, a control signal for changing the CPU's operation mode in accordance with a determination result obtained by the condition determiner. The disclosed system can reduce the operating frequency of a CPU or halt the operation of the CPU in accordance with an appropriate timing even when asynchronous communication is performed with peripheral devices.