| 摘要 |
PCT No. PCT/JP96/02018 Sec. 371 Date Jun. 19, 1997 Sec. 102(e) Date Jun. 19, 1997 PCT Filed Jul. 19, 1996 PCT Pub. No. WO97/04458 PCT Pub. Date Feb. 6, 1997A semiconductor memory device that steps up word lines, each of whose length is short enough to stay within one of the blocks that is formed by dividing a memory cell array into multiple blocks. The device includes multiple memory cells connected to pairs of bit lines and word lines at intersections of the pairs of bit lines and the word lines. Multiple memory cell array blocks are formed by dividing the region where the memory cells are arranged into blocks. A first step-up line is commonly used in stepping-up the word lines. A step-up circuit is constructed of a step-up capacitor, which is connected to the first step-up line and a switching transistor, which precharges the step-up capacitor. The semiconductor memory device also has a step-up control circuit that outputs a precharge control signal, which precharges the step-up capacitor by ON driving the switching transistor, and a step-up driving signal, which changes the potential of the negative terminal of the step-up capacitor of the step-up circuit. Further, a second step-up line is provided in each memory cell array block. During operation, a single memory cell array block is selected by a block selective circuit and a single word line is selected by row selective circuits. In this manner, the single selected word line within the single selected memory cell array block is stepped up by means of the first and second step-up lines.
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