| 摘要 |
Integrated circuits having improved electrostatic discharge capability include MOS transistors having wide channel widths formed by patterning a plurality of MOS transistor cells side-by-side in a well region as a highly integrated ladder network. The drain regions of the MOS transistor cells are coupled to an input pad to be protected and the source regions of the MOS transistor cells are coupled to a reference signal line (e.g., GND, VSS). The gate electrodes of the MOS transistor cells are also coupled together and indirectly through the well region to the reference signal line. The gates electrodes are coupled to the well region so that at the onset of reverse P-N junction breakdown between one or more of the drain regions (e.g., N-type) and the well region (e.g., P-type), the potentials of the gate electrodes of the MOS transistor cells are increased. This increase in gate electrode potential causes the breakdown voltages of the other nonconducting drain regions to be lowered to initiate breakdown so that the electrostatic discharge current can be more uniformly shared by all of the MOS transistor cells.
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