发明名称 Processor using implicit register addressing
摘要 To obtain a high performance computer decreased in the number of commands to be executed. A control circuit receives a command (CMD), and outputs a special command signal which becomes "H" when the command (CMD) instructs "push" command, to a register file. The register file, when the special command signal is "H", outputs the stored data value of register as register data regardless of the values of read register address signals, and and outputs the stored data value of register as register data. An ALU adds the register data and control data, and outputs the ALU operation result to the register file. An address adder adds the register data and control data, and outputs the address addition result to an external memory.
申请公布号 US5875323(A) 申请公布日期 1999.02.23
申请号 US19950547798 申请日期 1995.10.25
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 MACHIDA, HIROHISA
分类号 G06F9/38;G06F9/30;G06F9/32;G06F9/34;G06F9/42;(IPC1-7):G06F9/302 主分类号 G06F9/38
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