发明名称 |
Delay adjustment circuit in a performance monitoring and test system |
摘要 |
A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.
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申请公布号 |
US5875217(A) |
申请公布日期 |
1999.02.23 |
申请号 |
US19950452347 |
申请日期 |
1995.05.26 |
申请人 |
APPLIED DIGITAL ACCESS |
发明人 |
HARTMANN, PAUL R.;POPE, KEVIN;CADIEUX, KEVIN |
分类号 |
H04J3/06;H04J3/14;H04M3/22;H04M3/24;(IPC1-7):H04L7/00 |
主分类号 |
H04J3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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