| 摘要 |
<p>A timing generator which can preset data for generating a timing signal in the next cycle even when test pattern signals are generated in a multiway system. Each of clock data processing circuits of N timing generators (where N is an integer of 2 or above) is provided with a multiplier which multiplies the value of periodic data read out of a periodic data memory of the clock data processing circuit by N, a subtractor which performs subtraction on the periodic data muliplied by N by means of the multiplier and the clock data supplied from a main controller, and a means for giving the clock data processing circuit a control signal that enables a next flag, which is outputted from the carry signal output terminal of the subtractor when the value of the clock data is larger than the subtracted value outputted from the output terminal of the subtractor and the value of the periodic data multiplied by N only when N periodic data each having a definite period are continuously outputted and which indicates the generation of a clock in the next cycle, to be stored in the memory of the corresponding clock generator.</p> |
