发明名称 |
Clock-synchronised single-chip memory device |
摘要 |
The memory device has a memory divided into an ordinary memory region (2) and a memory region (4) storing sequential logic data, e.g, control signals, data signals and address signals. A data control circuit (3) and a logic data control circuit (1,5-7) receive and store the data values and the logic data values in the ordinary memory region and the logic data memory region respectively.
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申请公布号 |
DE19808337(A1) |
申请公布日期 |
1999.02.18 |
申请号 |
DE19981008337 |
申请日期 |
1998.02.27 |
申请人 |
MITSUBISHI DENKI K.K., TOKIO/TOKYO, JP |
发明人 |
TOMIOKA, TAKANORI, TOKIO/TOKYO, JP |
分类号 |
G06F11/22;G11C29/36;(IPC1-7):G11C29/00 |
主分类号 |
G06F11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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