SYSTEM AND METHOD FOR GENERATING AND USING STAGE-BASED CONSTRAINTS FOR TIMING-DRIVEN DESIGN

摘要

An integrated circuit design is divided into partitions (108) which each contain two stages of information. The first stage corresponds to sources within the design (106), and the second stage corresponds to targets within the design (106). In one implementation, all of the sources in each partition are triggered by a common clock edge. In another implementation, all targets of each partition are triggered by a common clock edge. Specifying timing constraints in partitions (110) can provide an efficient method of determining how much slack, if any, is present in the timing of a design.