发明名称 Korrelationsberechnungseinrichtung
摘要 <p>In a correlation computing device including circuits for segmenting (1, 2, 3) a digital input signal into two kinds of digital signals according to a predetermined rule, arithmetically processing (4, 6) the two digital signals for each of the segments, and cumulatively adding (7) the results of signal processing for each of the segments, a high-order bit elimination circuit (9) is provided for eliminating high-order bits of the digital input signal prior to the signal processing.</p>
申请公布号 DE69032548(T2) 申请公布日期 1999.02.18
申请号 DE1990632548T 申请日期 1990.03.14
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., KADOMA, OSAKA, JP 发明人 UOMORI, KENYA, KATANO-SHI, JP;ISHII, HIROFUMI, MORIGUCHI-SHI, JP;MORIMURA, ATSUSHI, 540-10 GAKUENNAKA 4-CHOME, NARA-SHI, JP
分类号 H04N19/50;G06F17/15;G06T7/00;G06T7/20;H04N19/423;H04N19/426;H04N19/51;H04N19/527;H04N19/537;H04N19/547;H04N19/80;H04N19/85;(IPC1-7):G06F17/15 主分类号 H04N19/50
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