摘要 |
<p>In a correlation computing device including circuits for segmenting (1, 2, 3) a digital input signal into two kinds of digital signals according to a predetermined rule, arithmetically processing (4, 6) the two digital signals for each of the segments, and cumulatively adding (7) the results of signal processing for each of the segments, a high-order bit elimination circuit (9) is provided for eliminating high-order bits of the digital input signal prior to the signal processing.</p> |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., KADOMA, OSAKA, JP |
发明人 |
UOMORI, KENYA, KATANO-SHI, JP;ISHII, HIROFUMI, MORIGUCHI-SHI, JP;MORIMURA, ATSUSHI, 540-10 GAKUENNAKA 4-CHOME, NARA-SHI, JP |