发明名称 DESIGN RULE CHECK METHOD IN LAYOUT DATA FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND DEVICE FOR EXECUTING THE SAME
摘要 PROBLEM TO BE SOLVED: To automatically execute a processing for removing a 'pseudo error' occurred in a recessed part from error data at the time of executing design rule checking on layout data of a semiconductor integrated circuit and for extracting only a real error. SOLUTION: Error graphic data (d) and (e) [→(B)] which are judged to be rule violation and are outputted at the time of executing design rule checking on wirings (a) and (b) shown in (A) are enlargement-processed. When logical NOT is taken between enlarged graphic data and error graphic data (d) and (e), graphic data (f) [→(C)] is obtained. When logical NOT is taken between graphic data (f) and layout data (wrings (a) and (b)), data (g) and (h) [→(D)] is obtained. Then, only the real error can be extracted among respective pieces of error graphic data by extracting data except for data which is brought into contact with only one data (g) or (h) from error graphic data (d) and (e).
申请公布号 JPH1139365(A) 申请公布日期 1999.02.12
申请号 JP19970195666 申请日期 1997.07.22
申请人 NEC CORP 发明人 HARADA MASANAO
分类号 H01L21/82;G06F17/50;(IPC1-7):G06F17/50 主分类号 H01L21/82
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