发明名称 POWER SAVING CONTROL CIRCUIT FOR CPU
摘要 <p>PROBLEM TO BE SOLVED: To prevent an unintentional interruption of a program operation by providing a control means for controlling the permission/non-permission of the power saving control of CPU based on the activity detection result of CPU with the discrete value of a counter showing the number of programs in a parallel processing. SOLUTION: The register 101 of one bit, into which data '1' is written when a program processing that is not to be interrupted during the processing by CPU 3 and into which data '0' is written when the program during the processing is completed and the counter 102 adding or subtracting the number of writing signals by which CPU 3 writes data in the register 101 in accordance with data '1' or '0' that the register 101 holds and showing the number of programs during the parallel processing with the discrete value are provided. The control means 103 and 105 control the permission or non-permission of power saving control of CPU 3 based on the activity detection result of CPU 3 according as whether the discrete value of the counter 102 is zero or not.</p>
申请公布号 JPH1139064(A) 申请公布日期 1999.02.12
申请号 JP19970195463 申请日期 1997.07.22
申请人 OKI ELECTRIC IND CO LTD 发明人 NAGANO MASATO
分类号 G06F1/32;G06F1/26;G06F11/30;(IPC1-7):G06F1/26 主分类号 G06F1/32
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