发明名称 BIT SYNCHRONIZATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a bit synchronization circuit without needing a large and complicated control circuit, an analog device, etc., by setting the clock that has its changing point at a time having a phase different by about 180 degrees from the time of the changing point of the data on an input terminal as its own device clock that is supplied to a decision circuit. SOLUTION: The data inputted to a data waveform shaping circuit 1 are shaped into the data and the inverted data, and the shaped input data are branched out into two data. One of both branched data is inputted to a data conversion point detection circuit 2. The circuit 2 produces a pulse having the delay value width at a position that is coincident with a data conversion point in order to secure an exclusive OR (EXOR) between the data and the data delay component. At the same time, the clock that is inputted to a system is branched out into two clocks. One of both clocks is converted into an anti- phase component via an inverted buffer 74, and this converted component is transmitted through the delay buffers 70 and 71 to secure a phase difference. Then every anti-phase component is inputted to a clock rise detection circuit 3.
申请公布号 JPH1141220(A) 申请公布日期 1999.02.12
申请号 JP19970194281 申请日期 1997.07.18
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 YASUKAWA MASANAGA;YAMANAKA NAOAKI;KAWAMURA TOMOAKI;KAWANO RYUSUKE;SHIOMOTO KOHEI
分类号 H04L25/40;H04L7/02 主分类号 H04L25/40
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