CLOCK REPRODUCING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To perform clock reproduction for pull-in setting at a high speed in packet communication. SOLUTION: Two steps of logic gates 1 and 2 for AND and NAND outputs are provided, a clock string is inputted to one of AND and NAND logic gates on the 1st step, and the NAND outputs of the AND and NAND gates 1 and 2 on the 2nd step are delayed and inputted to the other input. The NAND output of the 1st step is delayed for a 1/2 bit and inputted to one input of the AND and NAND logic gates 1 and 2 on the 2nd step, and the AND output on the 1st step is inputted to the other input. The AND output on the 2nd step is defined as a clock reproducing output.