| 摘要 |
<p>A synchronous delay circuit includes a first delay circuit for propagating a pulse or pulse edge therethrough for a fixed period of time, a second delay circuit capable of passing a pulse or pulse edge over a length proportional to the length of the first delay circuit along which the pulse or pulse edge propagated, and a circuit for outputting a monitor signal for a period of time over which a clock pulse is propagating through a clock driver. The first delay circuit is constituted by a clocked inverter and propagation of the pulse or pulse edge through the first delay circuit is halted at any desired timing during the output of the monitor signal. <IMAGE></p> |
