| 摘要 |
<p>At thinning, under the condition that a second multiplexer is switched to output an output of a first adder and a third multiplexer is switched to output an output of a second adder, a first multiplexer is alternatively switched at every line. A delay circuit memorizes an added result of a one-line preceding input signal and a two-line preceding input signal, and the second adder outputs at every two lines an added result of image data of a present line, a one-line preceding line and a two-line preceding line. At interpolation, under the condition that the second multiplexer is switched to output the output of the delay circuit, the first multiplexer is alternatively switched to output one of the input signal and the output of the second multiplexer, and the second multiplexer is alternatively switched to output one of the output of the second adder and the output of the delay circuit. Thus, the delay circuit outputs at every two lines an added result of the one-line preceding input signal and the two-line preceding input signal, which leads to size reduction of a perpendicular thinning/interpolation circuit for an image signal. <IMAGE></p> |
