发明名称 A SYSTEM FOR SIGNAL PROCESSING USING MULTIPLY-ADD OPERATIONS
摘要 A computer system which includes a multimedia input device which generates an audio or video input signal and a processor coupled to the multimedia input device. The system further includes a storage device coupled to the processor and having stored therein a signal processing routine for multiplying and accumulating input values representative of the audio or video input signal. The signal processing routine, when executed by the processor, causes the processor to perform several steps. These steps include performing a packed multiply add on a first set of values packed into a first source and a second set of values packed into a second source each representing input signals to generate a packed intermediate result. The packed intermediate result is added to an accumulator to generate a packed accumulated result in the accumulator. These steps may be iterated with the first set of values and portions of the second set of values to the accumulator to generate the packed accumulated result. Subsequent thereto, the packed accumulated result in the accumulator is unpacked into a first result and a second result and the first result and the second result are added together to generate an accumulated result.
申请公布号 EP0870224(A4) 申请公布日期 1999.02.10
申请号 EP19960945274 申请日期 1996.12.24
申请人 INTEL CORPORATION 发明人 DULONG, CAROLE;MENNEMEIER, LARRY, M.;PELEG, ALEXANDER, D.;BUI, TUAN, H.;KOWASHI, EIICHI;MITTAL, MILLIND;EITAN, BENNY;FISHER, STEPHEN, A.;MAYTAL, BENNY
分类号 G06F7/544;G06F9/302;(IPC1-7):G06F7/38;G06F7/52;G06F15/00;G06F15/76;G06F15/78;G06F15/80 主分类号 G06F7/544
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