System and method for fetching multiple groups of instructions from an instruction cache in a RISC processor system for execution during separate cycles

摘要

A system and method for fetching instructions for use in a RISC processor having an on-chip instruction cache is disclosed. The system accesses a first group of instructions having a first set of ordered addresses and a second group of instructions having a second set of ordered addresses, simultaneously, from an instruction cache. The first group of instructions is to be executed during a first cycle and the second group of instructions is to be executed during a second cycle. The technique transfers the first group of instructions to an instruction decoder for execution during the first cycle and transfers the second group of instructions to the instruction decoder for execution during the second cycle. The technique reduces the power consumed by memory modules and support circuitry of the instruction cache by requiring instruction cache accesses only every other cycle.