Non-blocking memory write/read mechanism by combining two pending commands write and read in buffer and executing the combined command in advance of other pending command

摘要

A computer system is disclosed which has a plurality of masters, such as a processor, a cache memory or an I/O device controller. Read response time from the main memory is minimized by a read-from-write scheme which gives priority to read commands. If a read command is to access data with the same address of a previously issued but pending write command in the buffer of a memory controller, then the read and write commands are combined and the read/write command is given priority over each other pending read or write command. To further reduce mean read response time, the data to be written to the main memory is transferred directly from the buffer to the master which issued the read command contemporaneously with the execution of the write command on the main memory.