发明名称 |
Universal buffered interface for coupling multiple processors, memory units, and I/O interfaces to a common high-speed interconnect |
摘要 |
A multiprocessor data processing system includes a group of computational data processor nodes including at least one communication data processor node, at least one shared global memory with memory banks, and a number of bus interfaces each coupled between one of a set of local buses and a global bus. Each interface includes a number of input queues and output queues coupled between the local bus and the global bus. The interface supports the use of an inter-processor communication (IPC) mechanism that allows any processor to send an interrupt to any other processor in the system during a single global bus cycle. An interrupt mask is transferred over the address bus during a specially marked bus cycle, with the interrupt mask identifying the processor or processors to be interrupted for interprocessor communication.
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申请公布号 |
US5870572(A) |
申请公布日期 |
1999.02.09 |
申请号 |
US19960798186 |
申请日期 |
1996.12.23 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GARCIA, ARMANDO |
分类号 |
G06F13/24;G06F13/36;G06F13/38;G06F13/40;G06F13/42;G06F15/16;G06F15/17;(IPC1-7):G06F15/16 |
主分类号 |
G06F13/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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