发明名称 |
Method and apparatus for on die testing |
摘要 |
Circuits and methods of testing an integrated circuit die are disclosed. Active logic setting circuits are incorporated into input cells of a die. During testing, the active logic setting circuits weakly drive the input cells to a definite logic level. Therefore, the necessity of connecting probes to all of the input pads to prevent floating signals in the die is eliminated. Furthermore, during normal operations the active logic setting circuits have little or no effect on the performance of the die.
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申请公布号 |
US5870408(A) |
申请公布日期 |
1999.02.09 |
申请号 |
US19960641308 |
申请日期 |
1996.04.30 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
AGGARWAL, SANDEEP K.;BERTUCCI, DAVID F.;LEVITT, MARC E. |
分类号 |
G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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