发明名称 |
Metallization and wire bonding process for manufacturing power semiconductor devices |
摘要 |
A metallization and bonding process for manufacturing a power semiconductor device includes a step of depositing a first metal layer over the entire surface of a chip; a step of selectively etching of the first metal layer to form desired patterns of metal interconnection lines between components previously defined; a step of depositing a layer of passivating material over the entire surface of the chip; a step of selectively etching of the layer of passivating material down to the first metal layer to define bonding areas represented by uncovered portions of the first metal layer; a step of depositing of a thick second metal layer over the entire surface of the chip; a step of selectively etching of the second metal layer down to the layer of passivating material to remove the second metal layer outside the bonding areas; and a step of connecting bonding wires to the surface of the second metal layer in correspondence of said bonding areas.
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申请公布号 |
US5869357(A) |
申请公布日期 |
1999.02.09 |
申请号 |
US19960681621 |
申请日期 |
1996.07.29 |
申请人 |
CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO |
发明人 |
ZAMBRANO, RAFFAELE |
分类号 |
H01L23/52;H01L21/3205;H01L21/60;H01L21/768;H01L23/485;H01L29/417;H01L29/78;(IPC1-7):H01L21/283 |
主分类号 |
H01L23/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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