| 摘要 |
A digital receiver for receiving 8-bit permutable address code words. Before receiving each address code word the receiver must be activated by receiving five consecutive identical words of an interdigit signal of alternating 1's and 0's. The receiver must then receive the same address code word five times in succession in order to accept it. The incoming signals are applied to a 9-bit shift register. Each bit is counted by a counter, but if the bits in the first and ninth stages of the shift register are different, the counter is cleared. When the count in the counter indicates five identical 8-bit words have been received in succession and an interdigit detector detects that the word in the last eight stages of the shift register is an interdigit word, a state flip-flop is set activating the receiver. The next time the counter reaches a count indicating that five identical 8-bit words have been received in succession if the interdigit detector indicates that the word in the last eight stages of the shift register is not an interdigit word, a ready flip-flop is set latching the contents of the last eight stages of the shift register in a holding register.
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