| 摘要 |
<p>A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns, and a pair of complimentary digit lines being provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complimentary data lines. The data lines are coupled to respective inputs of a sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data is selectively coupled to the inputs of the sense amplifier from the complimentary digit lines for an addressed column. In a test mode, the multiplexer connects an I/O line for one array to one of the data lines and an I/O line for the other array to the other data line. Thus, in the test mode, data is simultaneously coupled to the inputs of the sense amplifier from respective digit lines of two different columns, thereby increasing the rate at which test data that has been written to the arrays can be read from the arrays.</p> |
