PLL FREQUENCY SYNTHESIZER AND METHOD FOR CONTROLLING THE PLL FREQUENCY SYNTHESIZER

摘要

A PLL frequency synthesizer which is provided with a voltage detector (9) which detects the present value of a control voltage applied to a voltage-controlled oscillator (6), a storage device (7) which stores in advance the set values of a plurality of control voltages corresponding to the set values of a plurality of frequency dividing numbers set in a frequency divider (2) and outputs the set value of the control voltage corresponding to the frequency dividing number set in the frequency divider by selecting the set value out of the set values of the control voltages, a voltage value comparator (8) which compares the present value of the control voltage detected by the detector (9) with the set value of the control voltage outputted from the device (7), and a switching circuit (10) which outputs either the phase difference signal generated by means of a phase comparator (3) and representing the phase difference between the phase of a frequency dividing signal outputted from the divider (2) and that of a reference frequency signal or the output signal of the comparator (8) by switching. The comparator (8) controls the circuit (10) so that a charge pump (4) can be driven with its own output signal when the difference between the present value of the detected control voltage and the set value of the control voltage from the device (7) is larger than a prescribed value or with the phase different signal from the phase comparator (3) when the difference is not larger than the prescribed value.