发明名称 Signalprozessor zur Kodierung
摘要 An efficient coding signal processor for encoding information signals input in a sequence of block units in a manner of unifying an amount of information at a unit of N frames (N / 1), which includes a block activity calculator (7, 7c) for calculating a block activity for every block of the information signals in a present frame, a frame activity calculator (20) for calculating a frame activity from the block activity of the block in the preceding frames, a code amount allocator (11, 11c) for allocating an amount of codes for every block in the encoding process using the predicted frame activity, and a code amount allocation controller (24, 24c) for controlling the amount of codes to be allocated for every block up to a preselected bit rate by monitoring the amount of codes allocated by the code amount allocator for the period of one frame. <IMAGE>
申请公布号 DE69227970(D1) 申请公布日期 1999.02.04
申请号 DE1992627970 申请日期 1992.10.01
申请人 KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP 发明人 SHIMODA, KENJI, C/O INTELLECTUAL PROPERTY DIV., TOKYO, JP
分类号 H03M7/30;G06T9/00;H04N7/26;H04N7/30;H04N7/50;H04N11/04;(IPC1-7):H04N7/30 主分类号 H03M7/30
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