发明名称 VARIABLE WORD LENGTH MEMORY ACCESS SYSTEM
摘要 PROBLEM TO BE SOLVED: To obtain a variable word length memory access system which enables inexpensive variable word length memory access by designating a requested input-output bit number with a block number signal and deciding the number of memory blocks which are activated based on the signal. SOLUTION: A memory part which has 4Mb capacity consists of four 1Mb blocks 1 to 4. Each of blocks 1 to 4 enables 8-bit data input-output. The number of input-output bits that are requested is designated by a block number signal 22. The number of memory blocks that are activated is decided based on the signal 22, and a data signal is transferred. The transfer includes both cases of wiring to a memory block and of reading from a memory block. In this way, an output bit number of a memory macro block can be switched. Also, the smaller an output bit number is, the smaller the number of small blocks that are simultaneously activated is, and therefore, excessive power consumption can be avoided.
申请公布号 JPH1124989(A) 申请公布日期 1999.01.29
申请号 JP19970181229 申请日期 1997.07.07
申请人 NEC CORP 发明人 KIMURA TORU
分类号 G06F12/06;G11C7/10;(IPC1-7):G06F12/06 主分类号 G06F12/06
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