发明名称 CLOCK ADJUSTING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To adjust both the phase and pulse width of a balance transmit clock to conform with a reference clock waveform without any human intervention. SOLUTION: This circuit includes phase comparing circuits 13 and 14 which detect the phase shifts between the reference clock REF and the feedback FB of the clock output, counters 15 and 16 which count up respectively according to the phase shifts detected by the phase comparing circuits 13 and 14, and delay circuits 11 and 12 which delay the clock inputs according to the count values of the counters 15 and 16. One of the AND and OR outputs of the outputs of the delay circuits 11 and 12 is selected by a selector 23 to obtain the clock output.</p>
申请公布号 JPH1124783(A) 申请公布日期 1999.01.29
申请号 JP19970174141 申请日期 1997.06.30
申请人 NEC CORP 发明人 KOBAYASHI NAOKI
分类号 G06F1/10;H03K5/04;H03K5/13;H03L7/081;H03L7/087;(IPC1-7):G06F1/10 主分类号 G06F1/10
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